Direct memory access (DMA) has become a vital part of many high-end systems. For it allows additional bus masters to read or write system memory independently of the CPU(s).
By definition, DMA is a method of transferring data from the computer's RAM to another part of the computer without processing it using the CPU. While most data that is input or output from your computer is processed by the CPU, some data does not require processing, or can be processed by another device. In these situations, DMA can save processing time and is a more efficient way to move data from the computer's memory to other devices.
In other words, it is the capability to allow data to be sent directly from an attached device (such as a disk drive) to the memory on the computer's motherboard.
DMA channels can transfer blocks of data to or from devices with no CPU overhead. These blocks of memory are being copied from RAM to or from a buffer on the device. Such an operation usually does not stall the processor, which as a result can be scheduled to perform other tasks unless those tasks include a read from or write to memory.
But, though it is a more efficient way of moving data from the computer’s memory to other devices, it has also problems during caching memories.
As an effect of caching memory, DMA may lead to cache coherency problems. Cache coherency refers to the consistency of data stored in local caches of a shared resource.
Say for example, when the CPU accesses location X in the memory, the current value will be stored in the cache. Subsequent operations on X will update the cached copy of X, but not the external memory version of X. If the cache is not flushed to the memory before the next time a device tries to access X, the device will receive a stale value of X.
Similarly, if the cached copy of X is not invalidated when a device writes a new value to the memory, then the CPU will operate on a stale value of X.
Another problem that might occur is that when a device is programmed with an invalid physical address, the result is a bus error interrupt. The interrupt is taken by some CPU that is enabled for bus error interrupts. These interrupts are not simple to process for two reasons. First, the CPU that receives the interrupt is not necessarily the CPU from which the DMA operation was programmed. Second, the bus error can occur a long time after the operation was initiated.
Reference
TechTerms, n.d., ‘DMA (Direct Memory Access)’, viewed 3 September 2010,
Available at: <http://www.techterms.com/definition/dma>
Wikipedia, n. d., ‘Cache_coherence’, viewed 3 September 2010,
Available at : <http://en.wikipedia.org/wiki/Cache_coherence>
Russell Hitchcock, Dec 18, 2008, ‘Cache Coherency’, viewed 4 September 2010,
Physical and Virtual Memory, n.d., ‘Chapter 1. Physical and Virtual Memory’, viewed 4 September 2010,
Available at: <http://www.irixworld.net/library/SGI_bookshelves/SGI_Developer/books/DevDriver_PG/sgi_html/ch01.html>